Datasheet

1001
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
38.6.5.6 Interrupts
Depending on the interrupt mask in the PWM_IMR1 and PWM_IMR2 registers, an interrupt can be generated at
the end of the corresponding channel period (CHIDx in the PWM_ISR1 register), after a fault event (FCHIDx in the
PWM_ISR1 register), after a comparison match (CMPMx in the PWM_ISR2 register), after a comparison update
(CMPUx in the PWM_ISR2 register) or according to the transfer mode of the synchronous channels (WRDY,
ENDTX, TXBUFE and UNRE in the PWM_ISR2 register).
If the interrupt is generated by the flags CHIDx or FCHIDx, the interrupt remains active until a read operation in the
PWM_ISR1 register occurs.
If the interrupt is generated by the flags WRDY or UNRE or CMPMx or CMPUx, the interrupt remains active until a
read operation in the PWM_ISR2 register occurs.
A channel interrupt is enabled by setting the corresponding bit in the PWM_IER1 and PWM_IER2 registers. A
channel interrupt is disabled by setting the corresponding bit in the PWM_IDR1 and PWM_IDR2 registers.
38.6.5.7 Write Protect Registers
To prevent any single software error that may corrupt PWM behavior, the registers listed below can be write-
protected by writing the field WPCMD in the “PWM Write Protect Control Register” on page 1037 (PWM_WPCR).
They are divided into 6 groups:
 Register group 0:
 “PWM Clock Register” on page 1006
 Register group 1:
 “PWM Disable Register” on page 1008
 Register group 2:
 “PWM Sync Channels Mode Register” on page 1014
 “PWM Channel Mode Register” on page 1044
 “PWM Stepper Motor Mode Register” on page 1036
 Register group 3:
 “PWM Channel Period Register” on page 1048
 “PWM Channel Period Update Register” on page 1049
 Register group 4:
 “PWM Channel Dead Time Register” on page 1051
 “PWM Channel Dead Time Update Register” on page 1052
 Register group 5:
 “PWM Fault Mode Register” on page 1029
 “PWM Fault Protection Value Register” on page 1032
 “PWM Fault Protection Enable Register 1” on page 1033
 “PWM Fault Protection Enable Register 2” on page 1034
There are two types of Write Protect:
 Write Protect SW, which can be enabled or disabled.
 Write Protect HW, which can just be enabled, only a hardware reset of the PWM controller can disable it.
Both types of Write Protect can be applied independently to a particular register group by means of the WPCMD
and WPRG fields in PWM_WPCR register. If at least one Write Protect is active, the register group is write-
protected. The field WPCMD allows to perform the following actions depending on its value:
 0 = Disabling the Write Protect SW of the register groups of which the bit WPRG is at 1.
 1 = Enabling the Write Protect SW of the register groups of which the bit WPRG is at 1.
 2 = Enabling the Write Protect HW of the register groups of which the bit WPRG is at 1.