Datasheet

17.1.3 GIFR – General Interrupt Flag Register
Name: GIFR
Offset: 0x3A [ID-00000312]
Reset: 0
Property: When addressing I/O Registers as data space the offset address is 0x5A
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses.
Bit 7 6 5 4 3 2 1 0
INTF1 INTF0
Access
R/W R/W
Reset 0 0
Bit 7 – INTF1 External Interrupt Flag 1
When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in
SREG and the INT1 bit in GICR are set (one), the MCU will jump to the corresponding Interrupt Vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing
a logical one to it. This flag is always cleared when INT1 is configured as a level interrupt.
Bit 6 – INTF0 External Interrupt Flag 0
When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in
SREG and the INT0 bit in GICR are set (one), the MCU will jump to the corresponding Interrupt Vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing
a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt.
AVR 8-Bit Microcontroller
External Interrupts
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 79