Datasheet

14.8.1 MCUCR – MCU Control Register
Name: MCUCR
Offset: 0x35 [ID-00000e1c]
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x55
The MCU Control Register contains control bits for power management.
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses.
Bit 7 6 5 4 3 2 1 0
SE SMn[2:0]
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 5 – SE Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose,
it is recommended to set the Sleep Enable (SE) bit just before the execution of the SLEEP instruction.
Bits 4:2 – SMn[2:0] Sleep Mode n Select Bits [n=2:0]
These bits select between the five available sleep modes as shown in the table.
SM2 SM1 SM0 Sleep Mode
0 0 0 Idle
0 0 1 ADC Noise Reduction
0 1 0 Power-down
0 1 1 Power-save
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Standby
(1)
Note: 1. Standby mode is only available with external crystals or resonators.
AVR 8-Bit Microcontroller
Power Management and Sleep Modes
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 58