Datasheet

14.2 Idle Mode

When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping

the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial Interface, Timer/Counters,

Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clk

CPU

and

clk

FLASH

, while allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the

Timer Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator

interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the

Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle

mode. If the ADC is enabled, a conversion starts automatically when this mode is entered.

14.3 ADC Noise Reduction Mode

When the SM2:0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC Noise

Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the Two-wire Serial

Interface address watch, Timer/Counter2 and the Watchdog to continue operating (if enabled). This sleep

mode basically halts clk

I/O

, clk

CPU

, and clk

FLASH

, while allowing the other clocks to run.

This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC

is enabled, a conversion starts automatically when this mode is entered. Apart form the ADC Conversion

Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial

Interface address match interrupt, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, or an

external level interrupt on INT0 or INT1, can wake up the MCU from ADC Noise Reduction mode.

14.4 Power-down Mode

When the SM2:0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-down mode.

In this mode, the External Oscillator is stopped, while the external interrupts, the Two-wire Serial Interface

address watch, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog

Reset, a Brown-out Reset, a Two-wire Serial Interface address match interrupt, or an external level

interrupt on INT0 or INT1, can wake up the MCU. This sleep mode basically halts all generated clocks,

allowing operation of asynchronous modules only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level

must be held for some time to wake up the MCU. Refer to External Interrupts for details.

When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the

wake-up becomes effective. This allows the clock to restart and become stable after having been

stopped. The wake-up period is defined by the same CKSEL Fuses that define the Reset Time-out

period, as described in Clock Sources.