Datasheet

Symbol Parameter Condition Min Max Units
t
HD;STA
Hold Time (repeated) START
Condition
f
SCL
≤ 100kHz 4.0 – μs
f
SCL
> 100kHz 0.6 – μs
t
LOW
Low Period of the SCL Clock f
SCL
≤ 100kHz
(6)
4.7 – μs
f
SCL
> 100kHz
(7)
1.3 – μs
t
HIGH
High period of the SCL clock f
SCL
≤ 100kHz 4.0 – μs
f
SCL
> 100kHz 0.6 – μs
t
SU;STA
Set-up time for a repeated
START condition
f
SCL
≤ 100kHz 4.7 – μs
f
SCL
> 100kHz 0.6 – μs
t
HD;DAT
Data hold time f
SCL
≤ 100kHz 0 3.45 μs
f
SCL
> 100kHz 0 0.9 μs
t
SU;DAT
Data setup time f
SCL
≤ 100kHz 250 – ns
f
SCL
> 100kHz 100 – ns
t
SU;STO
Setup time for STOP condition f
SCL
≤ 100kHz 4.0 – μs
f
SCL
> 100kHz 0.6 – μs
t
BUF
Bus free time between a STOP
and START condition
f
SCL
≤ 100kHz 4.7 – μs
f
SCL
> 100kHz 1.3 – μs
Note:
1. In ATmega8A, this parameter is characterized and not 100% tested.
2. Required only for f
SCL
> 100kHz.
3. C
b
= capacitance of one bus line in pF.
4. f
CK
= CPU clock frequency
5. This requirement applies to all ATmega8A Two-wire Serial Interface operation. Other devices
connected to the Two-wire Serial Bus need only obey the general f
SCL
requirement.
6. The actual low period generated by the ATmega8A Two-wire Serial Interface is (1/f
SCL
- 2/f
CK
), thus
f
CK
must be greater than 6MHz for the low time requirement to be strictly met at f
SCL
= 100kHz.
7. The actual low period generated by the ATmega8A Two-wire Serial Interface is (1/f
SCL
- 2/f
CK
), thus
the low time requirement will not be strictly met for f
SCL
> 308kHz when f
CK
= 8MHz. Still,
ATmega8A devices connected to the bus may communicate at full speed (400kHz) with other
ATmega8A devices, as well as any other device with a proper t
LOW
acceptance margin.
Figure 30-3. Two-wire Serial Bus Timing
t
SU;STA
t
LOW
t
HIGH
t
LOW
t
of
t
HD;STA
t
HD;DAT
t
SU;DAT
t
SU;STO
t
BUF
SCL
SDA
t
r
AVR 8-Bit Microcontroller
Electrical Characteristics – TA = -40°C to 8...
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 312