Datasheet

11. AVR CPU Core

11.1 Overview

This section discusses the AVR core architecture in general. The main function of the CPU core is to

ensure correct program execution. The CPU must therefore be able to access memories, perform

calculations, control peripherals, and handle interrupts.

Figure 11-1. Block Diagram of the AVR MCU Architecture

Flash program

memory

Program

counter

Instruction

decode

Data memory

ALU

Status

R0R1

R2R3

R4R5

R6R7

R8R9

R10R11

R12R13

R14R15

R16R17

R18R19

R20R21

R22R23

R24R25

R26 (XL)R27 (XH)

R28 (YL)R29 (YH)

R30 (ZL)R31 (ZH)

Stack

pointer

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate

memories and buses for program and data. Instructions in the Program memory are executed with a

single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the

Program memory. This concept enables instructions to be executed in every clock cycle. The Program

memory is In-System Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock

cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU

operation, two operands are output from the Register File, the operation is executed, and the result is

stored back in the Register File – in one clock cycle.

AVR 8-Bit Microcontroller

AVR CPU Core

Datasheet Complete

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