Datasheet

23.5.2 SPSR – SPI Status Register

Name: SPSR

Offset: 0x0E [ID-000004d0]

Reset: 0x00

Property: When addressing I/O Registers as data space the offset address is 0x2E

When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When

addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset

addresses.

Bit 7 6 5 4 3 2 1 0

SPIF WCOL SPI2X

Access

R R R/W

Reset 0 0 0

Bit 7 – SPIF SPI Interrupt Flag

When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set

and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this

will also set the SPIF Flag. SPIF is cleared by hardware when executing the corresponding interrupt

handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF

set, then accessing the SPI Data Register (SPDR).

Bit 6 – WCOL Write Collision Flag

The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and

the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing the

SPI Data Register.

Bit 0 – SPI2X Double SPI Speed Bit

When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in

Master mode (refer to Table 23-5). This means that the minimum SCK period will be two CPU clock

periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f

osc

/4 or lower.

The SPI interface on the ATmega8A is also used for program memory and EEPROM downloading or

uploading. Refer to section Serial Downloading for serial programming and verification.