Datasheet

22.11.6 TIFR – Timer/Counter Interrupt Flag Register

Name: TIFR

Offset: 0x38 [ID-00000d14]

Reset: 0x00

Property: When addressing I/O Registers as data space the offset address is 0x58

When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When

addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset

addresses.

Bit 7 6 5 4 3 2 1 0

OCF2 TOV2

Access

R/W R/W

Reset 0 0

Bit 7 – OCF2 Output Compare Flag 2

The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2 and the data in

OCR2 – Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding

interrupt Handling Vector. Alternatively, OCF2 is cleared by writing a logic one to the flag. When the I-bit

in SREG, OCIE2 (Timer/Counter2 Compare Match Interrupt Enable), and OCF2 are set (one), the Timer/

Counter2 Compare Match Interrupt is executed.

Bit 6 – TOV2 Timer/Counter2 Overflow Flag

The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware

when executing the corresponding interrupt Handling Vector. Alternatively, TOV2 is cleared by writing a

logic one to the flag. When the SREG I-bit, TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2

are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when

Timer/Counter2 changes counting direction at 0x00.

AVR 8-Bit Microcontroller

8-bit Timer/Counter2 with PWM and Asynchronous Ope...

Datasheet Complete

40001974A-page 171