Datasheet

continuously low and if set equal to TOP the output will be set to high for non-inverted PWM mode. For
inverted PWM the output will have the opposite logic values.
If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will
toggle with a 50% duty cycle.
21.10 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
T1
) is therefore shown as a clock
enable signal in the following figures. The figures include information on when Interrupt Flags are set, and
when the OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double
buffering). The next figure shows a timing diagram for the setting of OCF1x.
Figure 21-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
clk
Tn
(clk
I/O
/1)
OCFnx
clk
I/O
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
The next figure shows the same timing data, but with the prescaler enabled.
Figure 21-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f
clk_I/O
/8)
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O
/8)
The next figure shows the count sequence close to TOP in various modes. When using phase and
frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be
AVR 8-Bit Microcontroller
16-bit Timer/Counter1
© 2017 Microchip Technology Inc.
Datasheet Complete
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