Datasheet

For detailed timing information refer to Timer/Counter Timing Diagrams.
21.9.1 Normal Mode
The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting direction
is always up (incrementing), and no counter clear is performed. The counter simply overruns when it
passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In
normal operation the Timer/Counter Overflow Flag (TOV1) will be set in the same timer clock cycle as the
TCNT1 becomes zero. The TOV1 Flag in this case behaves like a 17th bit, except that it is only set, not
cleared. However, combined with the timer overflow interrupt that automatically clears the TOV1 Flag, the
timer resolution can be increased by software. There are no special cases to consider in the Normal
mode, a new counter value can be written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval
between the external events must not exceed the resolution of the counter. If the interval between events
are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the
capture unit.
The Output Compare units can be used to generate interrupts at some given time. Using the Output
Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of
the CPU time.
21.9.2 Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Register are used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value
(TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1
define the top value for the counter, hence also its resolution. This mode allows greater control of the
Compare Match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown below. The counter value (TCNT1) increases until a
Compare Match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared.
Figure 21-6. CTC Mode, Timing Diagram
TCNTn
OCnA
(Toggle)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1 4
Period
2 3
(COMnA[1:0] = 0x1)
An interrupt can be generated at each time the counter value reaches the TOP value by either using the
OCF1A or ICF1 Flag according to the register used to define the TOP value. If the interrupt is enabled,
the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a
value close to BOTTOM when the counter is running with none or a low prescaler value must be done
with care since the CTC mode does not have the double buffering feature. If the new value written to
OCR1A or ICR1 is lower than the current value of TCNT1, the counter will miss the Compare Match. The
counter will then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000
before the Compare Match can occur. In many cases this feature is not desirable. An alternative will then
AVR 8-Bit Microcontroller
16-bit Timer/Counter1
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Datasheet Complete
40001974A-page 126