Datasheet

A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e. counter
resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms
generated by the waveform generator.
The figure below shows a block diagram of the Output Compare unit. The small “n” in the register and bit
names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output Compare
unit (A/B). The elements of the block diagram that are not directly a part of the Output Compare unit are
gray shaded.
Figure 21-4. Output Compare Unit, Block Diagram
OCFnx (Int.Req.)
= (16-bit Comparator )
OCRnx Buffer (16-bit Register)
OCRnxH Buf. (8-bit)
OCnx
TEMP (8-bit)
DATA BUS (8-bit)
OCRnxL Buf. (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit)
COMnx1:0WGMn3:0
OCRnx (16-bit Register)
OCRnxH (8-bit) OCRnxL (8-bit)
Waveform Generator
TOP
BOTTOM
The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM)
modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is
disabled. The double buffering synchronizes the update of the OCR1x Compare Register to either TOP or
BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-
symmetrical PWM pulses, thereby making the output glitch-free.
The OCR1x Register access may seem complex, but this is not case. When the double buffering is
enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU
will access the OCR1x directly. The content of the OCR1x (Buffer or Compare) Register is only changed
by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and
ICR1 Register). Therefore OCR1x is not read via the High byte temporary register (TEMP). However, it is
a good practice to read the Low byte first as when accessing other 16-bit registers. Writing the OCR1x
Registers must be done via the TEMP Register since the compare of all 16-bit is done continuously. The
High byte (OCR1xH) has to be written first. When the High byte I/O location is written by the CPU, the
TEMP Register will be updated by the value written. Then when the Low byte (OCR1xL) is written to the
lower eight bits, the High byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x
Compare Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to Accessing 16-bit Registers.
AVR 8-Bit Microcontroller
16-bit Timer/Counter1
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 123