Datasheet

19.5 Operation
The counting direction is always up (incrementing), and no counter clear is performed. The counter
simply overruns when it passes its maximum 8-bit value (MAX = 0xFF) and then restarts from the bottom
(0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock
cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is
only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the
TOV0 Flag, the timer resolution can be increased by software. A new counter value can be written
anytime.
19.6 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
T0
) is therefore shown as a clock
enable signal in the following figures. The figures include information on when Interrupt Flags are set. The
following figure contains timing data for basic Timer/Counter operation. The figure shows the count
sequence close to the MAX value.
Figure 19-3. Timer/Counter Timing Diagram, No Prescaling
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn
MAX - 1 MAX BOTTOM BOTTOM + 1
The next figure shows the same timing data, but with the prescaler enabled.
Figure 19-4. Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O
/8)
TOVn
TCNTn
MAX - 1 MAX BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
19.7 Register Description
AVR 8-Bit Microcontroller
8-bit Timer/Counter0
© 2017 Microchip Technology Inc.
Datasheet Complete
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