Datasheet

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11),
an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01) or output low ({DDxn,
PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant
environment will not notice the difference between a strong high driver and a pull-up. If this is not the
case, the PUD bit in the SFIOR Register can be set to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user must use
either the tristate ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an
intermediate step.
The table below summarizes the control signals for the pin value.
Table 18-1. Port Pin Configurations
DDxn PORTxn PUD (in
SFIOR)
I/O Pull-up Comment
0 0 x Input No Tri-state (Hi-Z)
0 1 0 Input Yes Pxn will source current if
external pulled low.
0 1 1 Input No Tri-state (Hi-Z)
1 0 x Output No Output Low (Sink)
1 1 x Output No Output High (Source)
18.2.2 Reading the Pin Value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn
Register Bit. As shown in Figure 18-2, the PINxn Register bit and the preceding latch constitute a
synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the
internal clock, but it also introduces a delay. The next figure shows a timing diagram of the
synchronization when reading an externally applied pin value. The maximum and minimum propagation
delays are denoted t
pd,max
and t
pd,min
respectively.
Figure 18-3. Synchronization when Reading an Externally Applied Pin value
XXX in r17, PINx
0x00 0xFF
INSTRUCTIONS
SYNC LATCH
PINxn
r17
XXX
SYSTEM CLK
t
pd, max
t
pd, min
AVR 8-Bit Microcontroller
I/O Ports
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 82