Datasheet

17.1.2 GICR – General Interrupt Control Register
Name: GICR
Offset: 0x3B [ID-00000312]
Reset: 0
Property: When addressing I/O Registers as data space the offset address is 0x5B
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses.
Bit 7 6 5 4 3 2 1 0
INT1 INT0
Access
R/W R/W
Reset 0 0
Bit 7 – INT1 External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin
interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control
Register (MCUCR) define whether the external interrupt is activated on rising and/or falling edge of the
INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as
an output. The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 Interrupt
Vector.
Bit 6 – INT0 External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin
interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control
Register (MCUCR) define whether the external interrupt is activated on rising and/or falling edge of the
INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as
an output. The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt
Vector.
AVR 8-Bit Microcontroller
External Interrupts
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 78