Datasheet

2. When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in
ACSR).
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must
always allow the reference to start up before the output from the Analog Comparator or ADC is used. To
reduce power consumption in Power-down mode, the user can avoid the three conditions above to
ensure that the reference is turned off before entering Power-down mode.
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System and Reset Characteristics
15.4 Watchdog Timer
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1MHz. This is the typical
value at V
CC
= 5V. See characterization data for typical values at other V
CC
levels. By controlling the
Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in the figure below.
The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset
when it is disabled and when a Chip Reset occurs. Eight different clock cycle periods can be selected to
determine the reset period. If the reset period expires without another Watchdog Reset, the ATmega8A
resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to the
Watchdog Reset.
To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be followed when
the Watchdog is disabled. Refer to the description of the Watchdog Timer Control Register for details.
Figure 15-7. Watchdog Timer
WATCHDOG
OSCILLATOR
15.5 Timed Sequences for Changing the Configuration of the Watchdog Timer
The sequence for changing the Watchdog Timer configuration differs slightly between the safety levels.
Separate procedures are described for each level.
Assembly Code Example
WDT_off:
AVR 8-Bit Microcontroller
System Control and Reset
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Datasheet Complete
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