Datasheet

Mnemonic Operands Description Op Flags
C ← Rd(0)
ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V
SWAP Rd Swap Nibbles Rd(3..0) ↔ Rd(7..4) None
SBI A, b Set Bit in I/O Register I/O(A, b) ← 1 None
CBI A, b Clear Bit in I/O Register I/O(A, b) ← 0 None
BST Rr, b Bit Store from Register to T T ← Rr(b) T
BLD Rd, b Bit load from T to Register Rd(b) ← T None
BSET s Flag Set SREG(s) ← 1 SREG(s)
BCLR s Flag Clear SREG(s) ← 0 SREG(s)
SEC Set Carry C ← 1 C
CLC Clear Carry C ← 0 C
SEN Set Negative Flag N ← 1 N
CLN Clear Negative Flag N ← 0 N
SEZ Set Zero Flag Z ← 1 Z
CLZ Clear Zero Flag Z ← 0 Z
SEI Global Interrupt Enable I ← 1 I
CLI Global Interrupt Disable I ← 0 I
SES Set Signed Test Flag S ← 1 S
CLS Clear Signed Test Flag S ← 0 S
SEV Set Two’s Complement Overflow V ← 1 V
CLV Clear Two’s Complement Overflow V ← 0 V
SET Set T in SREG T ← 1 T
CLT Clear T in SREG T ← 0 T
SEH Set Half Carry Flag in SREG H ← 1 H
CLH Clear Half Carry Flag in SREG H ← 0 H
Table 35-5. MCU Control Instructions
Mnemonic
Operands Description Operation Flags
BREAK Break (See also in Debug interface description) None
NOP No Operation None
SLEEP Sleep (see also power management and sleep description) None
WDR Watchdog Reset (see also Watchdog Controller description) None
Note:
1. Cycle time for data memory accesses assume internal RAM access and are not valid for accesses
through the NVM controller. A minimum of one extra cycle must be added when accessing memory
through the NVM controller (such as Flash and EEPROM), but depending on simultaneous
accesses by other masters or the NVM controller state, there may be more than one extra cycle.
AVR 8-Bit Microcontroller
Instruction Set Summary
© 2017 Microchip Technology Inc.
Datasheet Complete
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