Datasheet

Mnemonic Operands Description Op Flags
LD Rd, Z Load Indirect Rd ← (Z) None
LD Rd, Z+ Load Indirect and Post-Increment Rd
Z
←
←
(Z)
Z+1
None
LD Rd, -Z Load Indirect and Pre-Decrement Z
Rd
←
←
Z - 1
(Z)
None
LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None
STS k, Rr Store Direct to Data Space (k) ← Rd None
ST X, Rr Store Indirect (X) ← Rr None
ST X+, Rr Store Indirect and Post-Increment (X)
X
←
←
Rr
X + 1
None
ST -X, Rr Store Indirect and Pre-Decrement X
(X)
←
←
X - 1
Rr
None
ST Y, Rr Store Indirect (Y) ← Rr None
ST Y+, Rr Store Indirect and Post-Increment (Y)
Y
←
←
Rr
Y + 1
None
ST -Y, Rr Store Indirect and Pre-Decrement Y
(Y)
←
←
Y - 1
Rr
None
STD Y+q, Rr Store Indirect with Displacement (Y + q) ← Rr None
ST Z, Rr Store Indirect (Z) ← Rr None
ST Z+, Rr Store Indirect and Post-Increment (Z)
Z
←
←
Rr
Z + 1
None
ST -Z, Rr Store Indirect and Pre-Decrement Z ← Z - 1 None
STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None
LPM Load Program Memory R0 ← (Z) None
IN Rd, A In From I/O Location Rd ← I/O(A) None
OUT A, Rr Out To I/O Location I/O(A) ← Rr None
PUSH Rr Push Register on Stack STACK ← Rr None
POP Rd Pop Register from Stack Rd ← STACK None
Table 35-4. Bit and Bit-Test Instructions
Mnemonic
Operands Description Op Flags
LSL Rd Logical Shift Left Rd(n+1)
Rd(0)
C
←
←
←
Rd(n)
0
Rd(7)
Z,C,N,V,H
LSR Rd Logical Shift Right Rd(n)
Rd(7)
C
←
←
←
Rd(n+1)
0
Rd(0)
Z,C,N,V
ROL Rd Rotate Left Through Carry Rd(0)
Rd(n+1)
C
←
←
←
C
Rd(n)
Rd(7)
Z,C,N,V,H
ROR Rd Rotate Right Through Carry Rd(7)
Rd(n)
←
←
C
Rd(n+1)
Z,C,N,V
AVR 8-Bit Microcontroller
Instruction Set Summary
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 389