Datasheet

Mnemonic Operands Description Op Flags
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC ← PC + 2 or 3 None
SBRS Rr, b Skip if Bit in Register Set if (Rr(b) = 1) PC ← PC + 2 or 3 None
SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b) = 0) PC ← PC + 2 or 3 None
SBIS A, b Skip if Bit in I/O Register Set If (I/O(A,b) =1) PC ← PC + 2 or 3 None
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ← PC + k + 1 None
BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ← PC + k + 1 None
BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None
BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None
BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None
BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None
BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None
BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None
BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None
BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None
BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None
BRLT k Branch if Less Than, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None
BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None
BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None
BRIE k Branch if Interrupt Enabled if (I = 1) then PC ← PC + k + 1 None
BRID k Branch if Interrupt Disabled if (I = 0) then PC ← PC + k + 1 None
Table 35-3. Data Transfer Instructions
Mnemonic
Operands Description Op Flags
MOV Rd, Rr Copy Register Rd ← Rr None
LDI Rd, K Load Immediate Rd ← K None
LDS Rd, k Load Direct from data space Rd ← (k) None
LD Rd, X Load Indirect Rd ← (X) None
LD Rd, X+ Load Indirect and Post-Increment Rd
X
←
←
(X)
X + 1
None
LD Rd, -X Load Indirect and Pre-Decrement X
Rd
←
←
X - 1
(X)
None
LD Rd, Y Load Indirect Rd ← (Y) None
LD Rd, Y+ Load Indirect and Post-Increment Rd
Y
←
←
(Y)
Y + 1
None
LD Rd, -Y Load Indirect and Pre-Decrement Y
Rd
←
←
Y - 1
(Y)
None
LDD Rd, Y+q Load Indirect with Displacement Rd ← (Y + q) None
AVR 8-Bit Microcontroller
Instruction Set Summary
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 388