Datasheet

35. Instruction Set Summary
Table 35-1. Arithmetic and Logic Instructions
Mnemonic Operands Description Op Flags
ADD Rd, Rr Add without Carry Rd ← Rd + Rr Z,C,N,V,S,H
ADC Rd, Rr Add with Carry Rd ← Rd + Rr + C Z,C,N,V,S,H
ADIW Rd, K Add Immediate to Word Rd + 1:Rd ← Rd + 1:Rd + K Z,C,N,V,S
SUB Rd, Rr Subtract without Carry Rd ← Rd - Rr Z,C,N,V,S,H
SUBI Rd, K Subtract Immediate Rd ← Rd - K Z,C,N,V,S,H
SBC Rd, Rr Subtract with Carry Rd ← Rd - Rr - C Z,C,N,V,S,H
SBCI Rd, K Subtract Immediate with Carry Rd ← Rd - K - C Z,C,N,V,S,H
SBIW Rd, K Subtract Immediate from Word Rd + 1:Rd ← Rd + 1:Rd - K Z,C,N,V,S
AND Rd, Rr Logical AND Rd ← Rd • Rr Z,N,V,S
ANDI Rd, K Logical AND with Immediate Rd ← Rd • K Z,N,V,S
OR Rd, Rr Logical OR Rd ← Rd v Rr Z,N,V,S
ORI Rd, K Logical OR with Immediate Rd ← Rd v K Z,N,V,S
EOR Rd, Rr Exclusive OR Rd ← Rd ⊕ Rr Z,N,V,S
COM Rd One’s Complement Rd ← $FF - Rd Z,C,N,V,S
NEG Rd Two’s Complement Rd ← $00 - Rd Z,C,N,V,S,H
SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V,S
CBR Rd,K Clear Bit(s) in Register Rd ← Rd • ($FFh - K) Z,N,V,S
INC Rd Increment Rd ← Rd + 1 Z,N,V,S
DEC Rd Decrement Rd ← Rd - 1 Z,N,V,S
TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V,S
CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V,S
SER Rd Set Register Rd ← $FF None
Table 35-2. Branch Instructions
Mnemonic
Operands Description Op Flags
RJMP k Relative Jump PC ← PC + k + 1 None
IJMP Indirect Jump to (Z) PC(15:0)
PC(21:16)
←
←
Z
0
None
RCALL k Relative Call Subroutine PC ← PC + k + 1 None
ICALL Indirect Call to (Z) PC(15:0)
PC(21:16)
←
←
Z
0
None
RET Subroutine Return PC ← STACK None
RETI Interrupt Return PC ← STACK I
CPSE Rd,Rr Compare, skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None
CP Rd,Rr Compare Rd - Rr Z,C,N,V,S,H
CPC Rd,Rr Compare with Carry Rd - Rr - C Z,C,N,V,S,H
CPI Rd,K Compare with Immediate Rd - K Z,C,N,V,S,H
AVR 8-Bit Microcontroller
Instruction Set Summary
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 387