Datasheet

sbi EECR, EEWE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1<<EEMWE); /* start EEPROM write */

EECR |= (1<<EEWE);

SREG = cSREG; /* restore SREG value (I-bit) */

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before

any pending interrupts, as shown in the following example.

Assembly Code Example

sei ; set global interrupt enable

sleep ; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

_enable_interrupt(); /* set global interrupt enable */

_SLEEP(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

Related Links

MEMPROG- Memory Programming

Interrupts

BTLDR - Boot Loader Support – Read-While-Write Self-Programming

11.7.1 Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After

four clock cycles, the Program Vector address for the actual interrupt handling routine is executed. During

this 4-clock cycle period, the Program Counter is pushed onto the Stack. The Vector is normally a jump to

the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a

multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs

when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles.

This increase comes in addition to the start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the

Program Counter (2 bytes) is popped back from the Stack, the Stack Pointer is incremented by 2, and the

I-bit in SREG is set.

AVR 8-Bit Microcontroller

AVR CPU Core

Datasheet Complete

40001974A-page 34