Datasheet

27.8.3 ADCL – ADC Data Register Low (ADLAR=0)

Name: ADCL

Offset: 0x04

Reset: 0x00

Property: When addressing I/O Registers as data space the offset address is 0x24

When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When

addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset

addresses.

When an ADC conversion is complete, the result is found in these two registers.

When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result

is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise,

ADCL must be read first, then ADCH.

The ADLAR bit and the MUXn bits in ADMUX affect the way the result is read from the registers. If

ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted.

Bit 7 6 5 4 3 2 1 0

ADCn[7:0]

Access

R R R R R R R R

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – ADCn[7:0] ADC Conversion Result [n = 7:0]

These bits represent the result from the conversion. Refer to ADC Conversion Result for details.

AVR 8-Bit Microcontroller

ADC - Analog to Digital Converter

Datasheet Complete

40001974A-page 268