Datasheet

first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in
order to initialize the analog circuitry.
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and
13.5 ADC clock cycles after the start of an first conversion. When a conversion is complete, the result is
written to the ADC Data Registers, and ADIF is set. In single conversion mode, ADSC is cleared
simultaneously. The software may then set ADSC again, and a new conversion will be initiated on the first
rising ADC clock edge.
In Free Running mode, a new conversion will be started immediately after the conversion completes,
while ADSC remains high. For a summary of conversion times, see Analog to Digital Converter Block
Schematic Operation.
Figure 27-3. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
Sample and Hold
ADIF
ADCH
ADCL
Cycle Number
ADEN
1 2
12
13
14 15
16 17
18 19 20 21 22
23
24 25
1 2
First Conversion
Next
Conversion
3
MUX and REFS
Update
MUX and REFS
Update
Conversion
Complete
Figure 27-4. ADC Timing Diagram, Single Conversion
1
2 3 4 5 6 7 8
9 10 11 12 13
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
1 2
One Conversion Next Conversion
3
Sample and Hold
MUX and REFS
Update
Conversion
Complete
MUX and REFS
Update
AVR 8-Bit Microcontroller
ADC - Analog to Digital Converter
© 2017 Microchip Technology Inc.
Datasheet Complete
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