Datasheet

Table 26-2. ACIS[1:0] Settings

ACIS1 ACIS0 Interrupt Mode

0 0 Comparator Interrupt on Output Toggle.

0 1 Reserved

1 0 Comparator Interrupt on Falling Output Edge.

1 1 Comparator Interrupt on Rising Output Edge.

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its

Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed.