Datasheet

25.8.5 TWAR – TWI (Slave) Address Register

Name: TWAR

Offset: 0x02

Reset: 0x7F

Property: When addressing I/O Registers as data space the offset address is 0x22

When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When

addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset

addresses.

The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of TWAR) to

which the TWI will respond when programmed as a Slave Transmitter or Receiver, and not needed in the

Master modes. In multimaster systems, TWAR must be set in masters which can be addressed as Slaves

by other Masters.

The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an

associated address comparator that looks for the slave address (or general call address if enabled) in the

received serial address. If a match is found, an interrupt request is generated.

Bit 7 6 5 4 3 2 1 0

TWAn[6:0] TWGCE

Access

R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 1 0

Bits 7:1 – TWAn[6:0] TWI (Slave) Address [n = 6:0]

These seven bits constitute the slave address of the TWI unit.

Bit 0 – TWGCE TWI General Call Recognition Enable Bit

If set, this bit enables the recognition of a General Call given over the Two-wire Serial Bus.

AVR 8-Bit Microcontroller

TWI - Two-wire Serial Interface

Datasheet Complete

40001974A-page 247