Datasheet
25.3.1 TWI Terminology
The following definitions are frequently encountered in this section.
Table 25-1. TWI Terminology
Term Description
Master The device that initiates and terminates a transmission. The Master also generates the SCL clock.
Slave The device addressed by a Master.
Transmitter The device placing data on the bus.
Receiver The device reading data from the bus.
25.3.2 Electrical Interconnection
As depicted in Figure 25-2, both bus lines are connected to the positive supply voltage through pull-up
resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements
a wired-AND function which is essential to the operation of the interface. A low level on a TWI bus line is
generated when one or more TWI devices output a zero. A high level is output when all TWI devices tri-
state their outputs, allowing the pull-up resistors to pull the line high. Note that all AVR devices connected
to the TWI bus must be powered in order to allow any bus operation.
The number of devices that can be connected to the bus is only limited by the bus capacitance limit of
400pF and the 7-bit slave address space. A detailed specification of the electrical characteristics of the
TWI is given in Two-wire Serial Interface Characteristics. Two different sets of specifications are
presented there, one relevant for bus speeds below 100kHz, and one valid for bus speeds up to 400kHz.
Related Links
Two-wire Serial Interface Characteristics
25.4 Data Transfer and Frame Format
25.4.1 Transferring Bits
Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level of the
data line must be stable when the clock line is high. The only exception to this rule is for generating start
and stop conditions.
Figure 25-3. Data Validity
SD
A
SCL
Data Stab le Data Stab le
Data Change
AVR 8-Bit Microcontroller
TWI - Two-wire Serial Interface
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 217