Datasheet

Figure 24-2. Clock Generation Logic, Block Diagram
Prescaling
Down-Counter
/2
UBRRn
/4 /2
foscn
UBRRn+1
Sync
Register
OSC
XCKn
Pin
txclk
U2Xn
UMSELn
DDR_XCKn
0
1
0
1
xcki
xcko
DDR_XCKn
rxclk
0
1
1
0
Edge
Detector
UCPOLn
Signal description:
txclk Transmitter clock (internal signal).
rxclk Receiver base clock (internal signal).
xcki Input from XCK pin (internal Signal). Used for synchronous slave operation.
xcko Clock output to XCK pin (internal signal). Used for synchronous master operation.
fosc XTAL pin frequency (System Clock).
24.3.1 Internal Clock Generation – The Baud Rate Generator
Internal clock generation is used for the asynchronous and the synchronous master modes of operation.
The description in this section refers to the block diagram above.
The USART Baud Rate Register (UBRR) and the down-counter connected to it function as a
programmable prescaler or baud rate generator. The down-counter, running at system clock (fosc), is
loaded with the UBRR value each time the counter has counted down to zero or when the UBRRL
Register is written. A clock is generated each time the counter reaches zero. This clock is the baud rate
generator clock output (= fosc/(UBRR+1)). The Transmitter divides the baud rate generator clock output
by 2, 8, or 16 depending on mode. The baud rate generator output is used directly by the Receiver’s
clock and data recovery units. However, the recovery units use a state machine that uses 2, 8, or 16
states depending on mode set by the state of the UMSEL, U2X and DDR_XCK bits.
The table below contains equations for calculating the baud rate (in bits per second) and for calculating
the UBRR value for each mode of operation using an internally generated clock source.
AVR 8-Bit Microcontroller
USART - Universal Synchronous and Asynchrono...
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