Datasheet

21.11.3 TCNT1L – Timer/Counter1 Low byte

Name: TCNT1L

Offset: 0x2C

Reset: 0x00

Property: When addressing I/O Registers as data space the offset address is 0x4C

When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When

addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset

addresses.

Bit 7 6 5 4 3 2 1 0

TCNT1L[7:0]

Access

R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – TCNT1L[7:0] Timer/Counter 1 Low byte

The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both

for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high

and low bytes are read and written simultaneously when the CPU accesses these registers, the access is

performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all

the other 16-bit registers. Refer to Accessing 16-bit Registers for details.

Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a compare match

between TCNT1 and one of the OCR1x Registers.

Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock for all

compare units.

AVR 8-Bit Microcontroller

16-bit Timer/Counter1

Datasheet Complete

40001974A-page 140