Datasheet

Both the Input Capture Pin (ICP1) and the Analog Comparator Output (ACO) inputs are sampled using
the same technique as for the T1 pin (see figure T1 Pin Sampling in section External Clock Source). The
edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted
before the edge detector, which increases the delay by four system clock cycles. Note that the input of
the noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform
Generation mode that uses ICR1 to define TOP.
An Input Capture can be triggered by software by controlling the port of the ICP1 pin.
Related Links
External Clock Source
21.6.2 Noise Canceler
The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise
canceler input is monitored over four samples, and all four must be equal for changing the output that in
turn is used by the edge detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in Timer/Counter
Control Register B (TCCR1B). When enabled the noise canceler introduces additional four system clock
cycles of delay from a change applied to the input, to the update of the ICR1 Register. The noise canceler
uses the system clock and is therefore not affected by the prescaler.
21.6.3 Using the Input Capture Unit
The main challenge when using the Input Capture unit is to assign enough processor capacity for
handling the incoming events. The time between two events is critical. If the processor has not read the
captured value in the ICR1 Register before the next event occurs, the ICR1 will be overwritten with a new
value. In this case the result of the capture will be incorrect.
When using the Input Capture interrupt, the ICR1 Register should be read as early in the interrupt handler
routine as possible. Even though the Input Capture interrupt has relatively high priority, the maximum
interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of
the other interrupt requests.
Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively
changed during operation, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each
capture. Changing the edge sensing must be done as early as possible after the ICR1 Register has been
read. After a change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a
logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not
required (if an interrupt handler is used).
21.7 Output Compare Units
The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If
TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag
(OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Compare Flag generates an
Output Compare interrupt. The OCF1x Flag is automatically cleared when the interrupt is executed.
Alternatively the OCF1x Flag can be cleared by software by writing a logical one to its I/O bit location.
The waveform generator uses the match signal to generate an output according to operating mode set by
the Waveform Generation mode (WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP
and BOTTOM signals are used by the waveform generator for handling the special cases of the extreme
values in some modes of operation (See Modes of Operation.)
AVR 8-Bit Microcontroller
16-bit Timer/Counter1
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 122