Datasheet

ATmega48PA/88PA/168PA [DATASHEET]

9223F–AVR–04/14

15.9.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register

• Bits 7:3 – Reserved

These bits are reserved bits in the Atmel

ATmega48PA/88PA/168PA and will always read as zero.

• Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag

The OCF0B bit is set when a compare match occurs between the Timer/Counter and the data in OCR0B – output compare

register0 B. OCF0B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively,

OCF0B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter compare B match

interrupt enable), and OCF0B are set, the Timer/Counter compare match interrupt is executed.

• Bit 1 – OCF0A: Timer/Counter 0 Output Compare A Match Flag

The OCF0A bit is set when a compare match occurs between the Timer/Counter0 and the data in OCR0A – output compare

register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0A

is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 compare match interrupt

enable), and OCF0A are set, the Timer/Counter0 compare match interrupt is executed.

• Bit 0 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the

corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-

bit, TOIE0 (Timer/Counter0 overflow interrupt enable), and TOV0 are set, the Timer/Counter0 overflow interrupt is executed.

The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 15-8 on page 93,

Section 15-8 “Waveform Generation Mode Bit Description” on page 93.

Bit 76543210

0x15 (0x35) –––––OCF0BOCF0ATOV0TIFR0

Read/Write R R R R R R/W R/W R/W

Initial Value00000000