Datasheet

265
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
28.8.2 Serial Programming Algorithm
When writing serial data to the Atmel
®
ATmega48PA/88PA/168PA, data is clocked on the rising edge of SCK.
When reading data from the Atmel ATmega48PA/88PA/168PA, data is clocked on the falling edge of SCK. See Figure 28-9
for timing details.
To program and verify the Atmel ATmega48PA/88PA/168PA in the serial programming mode, the following sequence is
recommended (see serial programming instruction set in Table 28-17 on page 266):
1. Power-up sequence:
Apply power between V
CC
and GND while RESET and SCK are set to “0”. In some systems, the programmer can
not guarantee that SCK is held low during power-up. In this case, RESET
must be given a positive pulse of at
least two CPU clock cycles duration after SCK has been set to “0”.
2. Wait for at least 20ms and enable serial programming by sending the programming enable serial instruction to pin
MOSI.
3. The serial programming instructions will not work if the communication is out of synchronization. When in sync.
the second byte (0x53), will echo back when issuing the third byte of the programming Enable instruction.
Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo
back, give RESET
a positive pulse and issue a new programming enable command.
4. The flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 6
LSB of the address and data together with the load program memory page instruction. To ensure correct loading
of the page, the data low byte must be loaded before data high byte is applied for a given address. The program
memory page is stored by loading the write program memory page instruction with the 7 MSB of the address. If
polling (RDY/BSY
) is not used, the user must wait at least t
WD_FLASH
before issuing the next page (See Table 28-
16). Accessing the serial programming interface before the flash write operation completes can result in incorrect
programming.
5. A: The EEPROM array is programmed one byte at a time by supplying the address and data together with the
appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is writ-
ten. If polling (RDY/BSY
) is not used, the user must wait at least t
WD_EEPROM
before issuing the next byte (see
Table 28-16). In a chip erased device, no 0xFFs in the data file(s) need to be programmed.
B: The EEPROM array is programmed one page at a time. The Memory page is loaded one byte at a time by sup-
plying the 6 LSB of the address and data together with the Load EEPROM memory page instruction. The
EEPROM memory page is stored by loading the write EEPROM memory page instruction with the 7 MSB of the
address. When using EEPROM page access only byte locations loaded with the load EEPROM memory page
instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY
) is not used, the used must
wait at least t
WD_EEPROM
before issuing the next byte (See Table 28-16). In a chip erased device, no 0xFF in the
data file(s) need to be programmed.
6. Any memory location can be verified by using the read instruction which returns the content at the selected
address at serial output MISO.
7. At the end of the programming session, RESET
can be set high to commence normal operation.
8. Power-off sequence (if needed):
Set RESET
to “1”.
Turn V
CC
power off.
Table 28-16. Typical Wait Delay Before Writing the Next Flash or EEPROM Location
Symbol Minimum Wait Delay
t
WD_FLASH
4.5ms
t
WD_EEPROM
3.6ms
t
WD_ERASE
9.0ms