Datasheet

249
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
27.9 Register Description
27.9.1 SPMCSR – Store Program Memory Control and Status Register
The store program memory control and status register contains the control bits needed to control the boot loader operations.
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the status register is set (one), the SPM ready interrupt will be enabled.
The SPM ready Interrupt will be executed as long as the SELFPRGEN bit in the SPMCSR register is cleared.
• Bit 6 – RWWSB: Read-While-Write Section Busy
When a self-programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set
(one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if
the RWWSRE bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will
automatically be cleared if a page load operation is initiated.
• Bit 5 – Reserved
This bit is a reserved bit in the Atmel
®
ATmega48PA/88PA/168PA and always read as zero.
• Bit 4 – RWWSRE: Read-While-Write Section Read Enable
When programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB
will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed
(SELFPRGEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SELFPRGEN, the next SPM
instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while the flash is
busy with a page erase or a page write (SELFPRGEN is set). If the RWWSRE bit is written while the flash is being loaded,
the flash load operation will abort and the data loaded will be lost.
• Bit 3 – BLBSET: Boot Lock Bit Set
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four clock cycles sets boot lock
bits and memory lock bits, according to the data in R0. The data in R1 and the address in the Z-pointer are ignored. The
BLBSET bit will automatically be cleared upon completion of the Lock bit set, or if no SPM instruction is executed within four
clock cycles.
An LPM instruction within three cycles after BLBSET and SELFPRGEN are set in the SPMCSR register, will read either the
lock bits or the fuse bits (depending on Z0 in the Z-pointer) into the destination register. See Section 27.8.9 “Reading the
Fuse and Lock Bits from Software” on page 243 for details.
• Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four clock cycles executes page
write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in
R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is executed
within four clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is addressed.
• Bit 1 – PGERS: Page Erase
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four clock cycles executes page
erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will
auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted
during the entire page write operation if the NRWW section is addressed.
Bit 7 6 5 4 3 2 1 0
0x37 (0x57) SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SELFPRGEN SPMCSR
Read/Write R/W R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0