Datasheet

ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
240
27.5 Boot Loader Lock Bits
If no boot loader capability is needed, the entire flash is available for application code. The boot loader has two separate sets
of boot lock bits which can be set independently. This gives the user a unique flexibility to select different levels of protection.
The user can select:
● To protect the entire flash from a software update by the MCU.
● To protect only the boot loader flash section from a software update by the MCU.
● To protect only the application flash section from a software update by the MCU.
● Allow software update in the entire flash.
See Table 27-2 and Table 27-3 for further details. The boot lock bits can be set in software and in serial or parallel
programming mode, but they can be cleared by a chip erase command only. The general write lock (lock bit mode 2) does
not control the programming of the flash memory by SPM instruction. Similarly, the general read/write lock (lock bit mode 1)
does not control reading nor writing by LPM/SPM, if it is attempted.
27.6 Entering the Boot Loader Program
Entering the boot loader takes place by a jump or call from the application program. This may be initiated by a trigger such
as a command received via USART, or SPI interface. Alternatively, the boot reset fuse can be programmed so that the reset
vector is pointing to the boot flash start address after a reset. In this case, the boot loader is started after a reset. After the
application code is loaded, the program can start executing the application code. Note that the fuses cannot be changed by
the MCU itself. This means that once the boot reset fuse is programmed, the reset vector will always point to the boot loader
reset and the fuse can only be changed through the serial or parallel programming interface.
Table 27-2. Boot Lock Bit0 Protection Modes (Application Section)
(1)
BLB0 Mode BLB02 BLB01 Protection
1 1 1 No restrictions for SPM or LPM accessing the application section.
2 1 0 SPM is not allowed to write to the application section.
3 0 0
SPM is not allowed to write to the application section, and LPM executing
from the boot loader section is not allowed to read from the application
section. If interrupt vectors are placed in the boot loader section, interrupts
are disabled while executing from the application section.
4 0 1
LPM executing from the boot loader section is not allowed to read from the
application section. If Interrupt Vectors are placed in the boot loader section,
interrupts are disabled while executing from the application section.
Note: 1. “1” means unprogrammed, “0” means programmed
Table 27-3. Boot Lock Bit1 Protection Modes (Boot Loader Section)
(1)
BLB1 Mode BLB12 BLB11 Protection
1 1 1 No restrictions for SPM or LPM accessing the boot loader section.
2 1 0 SPM is not allowed to write to the boot loader section.
3 0 0
SPM is not allowed to write to the boot loader section, and LPM executing
from the application section is not allowed to read from the boot loader
section. If interrupt vectors are placed in the application section, interrupts
are disabled while executing from the boot loader section.
4 0 1
LPM executing from the application section is not allowed to read from the
boot loader section. If interrupt vectors are placed in the application section,
interrupts are disabled while executing from the boot loader section.
Note: 1. “1” means unprogrammed, “0” means programmed