Datasheet

217
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
Figure 24-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Figure 24-5. ADC Timing Diagram, Single Conversion
1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3
Cycle Number
First Conversion
Sign and MSB of Result
LSB of Result
Next
Conversion
MUX and REFS
Update
Conversion
Complete
MUX and REFS
Update
ADC Clock
ADEN
ADSC
ADIF
ADCH
ADCL
Sample and Hold
12345678910111213 123
Cycle Number
One Conversion
Sign and MSB of Result
LSB of Result
Next Conversion
MUX and REFS
Update
Conversion
Complete
MUX and REFS
Update
ADC Clock
ADSC
ADIF
ADCH
ADCL
Sample and Hold