Datasheet

ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
212
• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the analog comparator interrupt. The different settings are shown
in Table 23-2.
When changing the ACIS1/ACIS0 bits, the analog comparator interrupt must be disabled by clearing its Interrupt Enable bit
in the ACSR register. Otherwise an interrupt can occur when the bits are changed.
23.3.3 DIDR1 – Digital Input Disable Register 1
• Bit 7:2 – Reserved
These bits are unused bits in the Atmel
®
ATmega48PA/88PA/168PA, and will always read as zero.
• Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding PIN register bit will
always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin
is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.
Table 23-2. ACIS1/ACIS0 Settings
ACIS1 ACIS0 Interrupt Mode
0 0 Comparator interrupt on output toggle
0 1 Reserved
1 0 Comparator interrupt on falling output edge
1 1 Comparator interrupt on rising output edge
Bit 76543210
(0x7F) ––––––AIN1DAIN0DDIDR1
Read/Write RRRRRRR/WR/W
Initial Value00000000