Datasheet

153
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
Figure 20-1. USART Block Diagram
(1)
Note: 1. Refer to Figure 1-1 on page 3 and Table 14-9 on page 76 for USART0 pin placement.
20.3 Clock Generation
The clock generation logic generates the base clock for the transmitter and receiver. The USART supports four modes of
clock operation: Normal asynchronous, double speed asynchronous, master synchronous and slave synchronous mode.
The UMSELn bit in USART Control and Status Register C (UCSRnC) selects between asynchronous and synchronous
operation. Double speed (asynchronous mode only) is controlled by the U2Xn found in the UCSRnA register. When using
synchronous mode (UMSELn = 1), the data direction register for the XCKn pin (DDR_XCKn) controls whether the clock
source is internal (master mode) or external (slave mode). The XCKn pin is only active when using synchronous mode.
Transmit Shift Register
Receive Shift Register
Data
Recovery
Clock
Recovery
Parity
Checker
Parity
Generator
Pin
Control
TX
Control
Pin
Control
Pin
Control
RX
Control
UDRn (Transmit)
Transmitter
Clock Generator
Receiver
UCSRnA UCSRnCUCSRnB
Sync Logic
OSC
UDRn (Receive)
DATA BUS
Baud Rate Generator
UBRRn [H:L]
XCKn
RxDn
TxDn