Datasheet

ATmega48PA/88PA/168PA [DATASHEET]

9223F–AVR–04/14

7.7 Reset and Interrupt Handling

The AVR

provides several different interrupt sources. These interrupts and the separate reset vector each have a separate

program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic

one together with the global interrupt enable bit in the status register in order to enable the interrupt. Depending on the

program counter value, interrupts may be automatically disabled when boot lock bits BLB02 or BLB12 are programmed. This

feature improves software security. See Section 28. “Memory Programming” on page 251 for details.

The lowest addresses in the program memory space are by default defined as the reset and interrupt vectors. The complete

list of vectors is shown in Section 12. “Interrupts” on page 50. The list also determines the priority levels of the different

interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the

external interrupt request 0. The interrupt vectors can be moved to the start of the boot flash section by setting the IVSEL bit

in the MCU control register (MCUCR). Refer to Section 12. “Interrupts” on page 50 for more information. The reset vector

can also be moved to the start of the boot flash section by programming the BOOTRST fuse, see

Section 27. “Boot Loader Support – Read-While-Write Self-Programming” on page 237.

When an interrupt occurs, the global interrupt enable I-bit is cleared and all interrupts are disabled. The user software can

write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine.

The I-bit is automatically set when a return from interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these

interrupts, the program counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine,

and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit

position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt

flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more

interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding Interrupt flag(s) will be set and

remembered until the global interrupt enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily

have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any

pending interrupt is served.

Note that the status register is not automatically stored when entering an interrupt routine, nor restored when returning from

an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed

after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can

be used to avoid interrupts during the timed EEPROM write sequence.