Datasheet

ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
136
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Reading of the TCNT2 register shortly after wake-up from power-save may give an incorrect result. Since TCNT2 is
clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register synchronized to the
internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When waking up from power-
save mode, and the I/O clock (clk
I/O
) again becomes active, TCNT2 will read as the previous value (before entering
sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from power-save mode is
essentially unpredictable, as it depends on the wake-up time. The recommended procedure for reading TCNT2 is
thus as follows:
a. Write any value to either of the registers OCR2x or TCCR2x.
b. Wait for the corresponding update busy flag to be cleared.
c. Read TCNT2.
During asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes 3 processor
cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value
causing the setting of the interrupt flag. The output compare pin is changed on the timer clock and is not synchronized to the
processor clock.
18.10 Timer/Counter Prescaler
Figure 18-12. Prescaler for Timer/Counter2
The clock source for Timer/Counter2 is named clk
T2S
. clk
T2S
is by default connected to the main system I/O clock clk
IO
. By
setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin. This enables use of
Timer/Counter2 as a real time counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from port B. A
crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for
Timer/Counter2. The oscillator is optimized for use with a 32.768kHz crystal.
For Timer/Counter2, the possible prescaled selections are: clk
T2S
/8, clk
T2S
/32, clk
T2S
/64, clk
T2S
/128, clk
T2S
/256, and
clk
T2S
/1024. Additionally, clk
T2S
as well as 0 (stop) may be selected. Setting the PSRASY bit in GTCCR resets the prescaler.
This allows the user to operate with a predictable prescaler.
Timer/Counter2 Clock Source
clk
T2
clk
T2S
/8
clk
T2S
/32
clk
T2S
/64
clk
T2S
/128
clk
T2S
/256
clk
T2S
/1024
clk
I/O
TOSC1
AS2
PSRASY
clk
T2S
10-bit T/C Prescaler
0
Clear
CS20
CS21
CS22