Datasheet

ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
120
16.11.4 TCNT1H and TCNT1L – Timer/Counter1
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for
write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register
(TEMP). This temporary register is shared by all the other 16-bit registers.
See Section 16.3 “Accessing 16-bit Registers” on page 100
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a compare match between TCNT1
and one of the OCR1x registers.
Writing to the TCNT1 register blocks (removes) the compare match on the following timer clock for all compare units.
16.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A
16.11.6 OCR1BH and OCR1BL – Output Compare Register 1 B
The output compare registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match
can be used to generate an output compare interrupt, or to generate a waveform output on the OC1x pin.
The output compare registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when
the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This
temporary register is shared by all the other 16-bit registers. See Section 16.3 “Accessing 16-bit Registers” on page 100
16.11.7 ICR1H and ICR1L – Input Capture Register 1
The input capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the
analog comparator output for Timer/Counter1). The input capture can be used for defining the counter TOP value.
The input capture register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the
CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary
register is shared by all the other 16-bit registers. See Section 16.3 “Accessing 16-bit Registers” on page 100
Bit 76543210
(0x85) TCNT1[15:8] TCNT1H
(0x84) TCNT1[7:0] TCNT1L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
(0x89) OCR1A[15:8] OCR1AH
(0x88) OCR1A[7:0] OCR1AL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
(0x8B) OCR1B[15:8] OCR1BH
(0x8A) OCR1B[7:0] OCR1BL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
(0x87) ICR1[15:8] ICR1H
(0x86) ICR1[7:0] ICR1L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000