Datasheet

ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
116
Figure 16-13 shows the same timing data, but with the prescaler enabled.
Figure 16-13. Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O
/8)
16.11 Register Description
16.11.1 TCCR1A – Timer/Counter1 Control Register A
• Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A
• Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B
The COM1A1:0 and COM1B1:0 control the output compare pins (OC1A and OC1B respectively) behavior. If one or both of
the COM1A1:0 bits are written to one, the OC1A output overrides the normal port functionality of the I/O pin it is connected
to. If one or both of the COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the I/O
pin it is connected to. However, note that the data direction register (DDR) bit corresponding to the OC1A or OC1B pin must
be set in order to enable the output driver.
When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is dependent of the WGM13:0 bits
setting. Table 16-2 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to a normal or a CTC mode (non-
PWM).
TOP - 1 TOP BOTTOM BOTTOM + 1
TOP - 1 TOP TOP - 1 TOP - 2
clk
I/O
(clk
I/O
/8)
TCNTn
(CTC and FPWM)
OCRnx
(Update at TOP)
TCNTn
(PC and PFC PWM)
TOVn (FPWM)
and ICFn
(if used as TOP)
clk
Tn
Old OCRnx Value New OCRnx Value
Bit 7 6 5 43210
(0x80) COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 TCCR1A
Read/Write R/W R/W R/W R/W R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 16-2. Compare Output Mode, non-PWM
COM1A1/COM1B1 COM1A0/COM1B0 Description
0 0 Normal port operation, OC1A/OC1B disconnected.
0 1 Toggle OC1A/OC1B on compare match.
1 0 Clear OC1A/OC1B on compare match (set output to low level).
1 1 Set OC1A/OC1B on compare match (set output to high level).