Datasheet

ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
90
15.8 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
T0
) is therefore shown as a clock enable signal in the
following figures. The figures include information on when interrupt flags are set. Figure 15-8 contains timing data for basic
Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase
correct PWM mode.
Figure 15-8. Timer/Counter Timing Diagram, no Prescaling
Figure 15-9 shows the same timing data, but with the prescaler enabled.
Figure 15-9. Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O
/8)
Figure 15-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where
OCR0A is TOP.
Figure 15-10.Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f
clk_I/O
/8)
MAX - 1
clk
I/O
(clk
I/O
/1)
TCNTn
TOVn
clk
Tn
MAX BOTTOM BOTTOM + 1
MAX - 1
clk
I/O
(clk
I/O
/8)
TCNTn
TOVn
clk
Tn
MAX BOTTOM BOTTOM + 1
OCRnx - 1
clk
I/O
(clk
I/O
/8)
TCNTn
OCRnx
OCFnx
clk
Tn
OCRnx OCRnx + 1
OCRnx Value
OCRnx + 2