Datasheet

ATmega48PA/88PA/168PA [DATASHEET]

9223F–AVR–04/14

14. I/O-Ports

14.1 Overview

All AVR

ports have true read-modify-write functionality when used as general digital I/O ports. This means that the direction

of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI

instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors

(if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability.

The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with

a supply-voltage invariant resistance. All I/O pins have protection diodes to both V

and ground as indicated in

Figure 14-1. Refer to Section 29. “Electrical Characteristics” on page 268 for a complete list of parameters.

Figure 14-1. I/O Pin Equivalent Schematic

All registers and bit references in this section are written in general form. A lower case “x” represents the numbering letter for

the port, and a lower case “n” represents the bit number. However, when using the register or bit defines in a program, the

precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The

physical I/O registers and bit locations are listed in Section 14.4 “Register Description” on page 79.

Three I/O memory address locations are allocated for each port, one each for the data register – PORTx, data direction

register – DDRx, and the port input pins – PINx. The port input pins I/O location is read only, while the data register and the

data direction register are read/write. However, writing a logic one to a bit in the PINx register, will result in a toggle in the

corresponding bit in the data register. In addition, the pull-up disable – PUD bit in MCUCR disables the pull-up function for all

pins in all ports when set.

Using the I/O port as general digital I/O is described in Section 14.2 “Ports as General Digital I/O” on page 65. Most port pins

are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with

the port pin is described in Section 14.3 “Alternate Port Functions” on page 69. Refer to the individual module sections for a

full description of the alternate functions.

Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as

general digital I/O.

Pxn

Logic

See Figure

”General Digital I/O”

for Details