Datasheet

ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
6
The AVR
®
core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly
connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in one single instruction
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times
faster than conventional CISC microcontrollers.
The Atmel
®
ATmega48PA/88PA/168PA provides the following features: 4K/8Kbytes of in-system programmable flash with
read-while-write capabilities, 256/512/512 bytes EEPROM, 512/1K/1Kbytes SRAM, 23 general purpose I/O lines, 32 general
purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial
programmable USART, a byte-oriented 2-wire serial interface, an SPI serial port, a 8-channel 10-bit ADC, a programmable
watchdog timer with internal oscillator, and five software selectable power saving modes. The idle mode stops the CPU while
allowing the SRAM, Timer/Counters, USART, 2-wire serial interface, SPI port, and interrupt system to continue functioning.
The power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next
interrupt or hardware reset. In power-save mode, the asynchronous timer continues to run, allowing the user to maintain a
timer base while the rest of the device is sleeping. The ADC Noise reduction mode stops the CPU and all I/O modules
except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In standby mode, the
crystal/resonator oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low
power consumption.
The device is manufactured using the Atmel high density non-volatile memory technology. The on-chip ISP flash allows the
program memory to be reprogrammed in-system through an SPI serial interface, by a conventional non-volatile memory
programmer, or by an on-chip boot program running on the AVR core. The boot program can use any interface to download
the application program in the application flash memory. Software in the boot flash section will continue to run while the
application flash section is updated, providing true read-while-write operation. By combining an 8-bit RISC CPU with in-
system self-programmable flash on a monolithic chip, the Atmel ATmega48PA/88PA/168PA is a powerful microcontroller
that provides a highly flexible and cost effective solution to many embedded control applications.
The Atmel ATmega48PA/88PA/168PA AVR is supported with a full suite of program and system development tools
including: C compilers, macro assemblers, program debugger/simulators, In-circuit emulators, and evaluation kits.
2.2 Comparison Between Processors
The Atmel ATmega48PA/88PA/168PA differ only in memory sizes, boot loader support, and interrupt vector sizes. Table 2-1
summarizes the different memory and interrupt vector sizes for the devices.
The Atmel ATmega48PA/88PA/168PA support a real read-while-write self-programming mechanism. There is a separate
boot loader section, and the SPM instruction can only execute from there. In the Atmel ATmega48PA there is no read-While-
write support and no separate boot loader section. The SPM instruction can execute from the entire flash.
Table 2-1. Memory Size Summary
Device Flash EEPROM RAM Interrupt Vector Size
Atmel ATmega48PA/ 4K Bytes 256 Bytes 512 Bytes 1 instruction word/vector
Atmel ATmega88PA 8K Bytes 512 Bytes 1K Bytes 1 instruction word/vector
Atmel ATmega168PA 16K Bytes 512 Bytes 1K Bytes 2 instruction words/vector