Datasheet

ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
312
(0xBA) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 209
(0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3
TWPS1 TWPS0 208
(0xB8) TWBR 2-wire Serial Interface Bit Rate Register 206
(0xB7) Reserved
(0xB6) ASSR
EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB 142
(0xB5) Reserved
(0xB4) OCR2B Timer/Counter2 Output Compare Register B 141
(0xB3) OCR2A Timer/Counter2 Output Compare Register A 141
(0xB2) TCNT2 Timer/Counter2 (8-bit) 141
(0xB1) TCCR2B FOC2A FOC2B
WGM22 CS22 CS21 CS20 140
(0xB0) TCCR2A COM2A1 COM2A0 COM2B1 COM2B0
–WGM21WGM20137
(0xAF) Reserved
(0xAE) Reserved
(0xAD) Reserved
(0xAC) Reserved
(0xAB) Reserved
(0xAA) Reserved
(0xA9) Reserved
(0xA8) Reserved
(0xA7) Reserved
(0xA6) Reserved
(0xA5) Reserved
(0xA4) Reserved
(0xA3) Reserved
(0xA2) Reserved
(0xA1) Reserved
(0xA0) Reserved
(0x9F) Reserved
(0x9E) Reserved
(0x9D) Reserved
(0x9C) Reserved
(0x9B) Reserved
(0x9A) Reserved
(0x99) Reserved
(0x98) Reserved
31. Register Summary (Continued)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
2. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags.
The CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel
ATmega48PA/88PA/168PA is a complex microcontroller with more peripheral units than can be supported within the 64
location reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM,
only the ST/STS/STD and LD/LDS/LDD instructions can be used.
5. Only valid for the Atmel ATmega48PA/88PA/168PA.
6. BODS and BODSE only available for picoPower devices ATmega48PA/88PA/168PA