Datasheet

233
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
26.2.2 Reading the Fuse and Lock Bits from Software
It is possible to read both the fuse and lock bits from software. To read the Lock bits, load the Z-pointer with 0x0001 and set
the BLBSET and SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three CPU cycles after the
BLBSET and SELFPRGEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the destination register. The
BLBSET and SELFPRGEN bits will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed
within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLBSET and SELFPRGEN are
cleared, LPM will work as described in the instruction set manual.
The algorithm for reading the fuse low byte is similar to the one described above for reading the lock bits. To read the fuse
low byte, load the Z-pointer with 0x0000 and set the BLBSET and SELFPRGEN bits in SPMCSR. When an LPM instruction
is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the SPMCSR, the value of the fuse low
byte (FLB) will be loaded in the destination register as shown below.See Table 28-5 on page 253 for a detailed description
and mapping of the fuse low byte.
Similarly, when reading the fuse high byte (FHB), load 0x0003 in the Z-pointer. When an LPM instruction is executed within
three cycles after the BLBSET and SELFPRGEN bits are set in the SPMCSR, the value of the fuse high byte will be loaded
in the destination register as shown below. See Table 28-5 on page 253 for detailed description and mapping of the
extended fuse byte.
Similarly, when reading the Extended Fuse byte (EFB), load 0x0002 in the Z-pointer. When an LPM instruction is executed
within three cycles after the BLBSET and SELFPRGEN bits are set in the SPMCSR, the value of the Extended Fuse byte will
be loaded in the destination register as shown below. See Table 28-5 on page 253 for detailed description and mapping of
the extended fuse byte.
Fuse and Lock bits that are programmed, will be read as zero. Fuse and lock bits that are unprogrammed, will be read as
one.
26.2.3 Preventing Flash Corruption
During periods of low V
CC
, the flash program can be corrupted because the supply voltage is too low for the CPU and the
Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design
solutions should be applied.
A flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to
the Flash requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if
the supply voltage for executing instructions is too low.
Flash corruption can easily be avoided by following these design recommendations (one is sufficient):
1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by
enabling the internal brown-out detector (BOD) if the operating voltage matches the detection level. If not, an
external low V
CC
reset protection circuit can be used. If a reset occurs while a write operation is in progress, the
write operation will be completed provided that the power supply voltage is sufficient.
2. Keep the AVR core in power-down sleep mode during periods of low V
CC
. This will prevent the CPU from attempt-
ing to decode and execute instructions, effectively protecting the SPMCSR register and thus the flash from
unintentional writes.
Bit 76543210
Rd ––––––LB2LB1
Bit 76543210
Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0
Bit 76543210
Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0
Bit 76543210
Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0