Datasheet

209
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
22.9.5 TWAR – TWI (Slave) Address Register
The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the TWI will
respond when programmed as a slave transmitter or receiver, and not needed in the master modes. In multi master
systems, TWAR must be set in masters which can be addressed as slaves by other masters.
The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an associated address
comparator that looks for the slave address (or general call address if enabled) in the received serial address. If a match is
found, an interrupt request is generated.
• Bits 7:1 – TWA: TWI (Slave) Address Register
These seven bits constitute the slave address of the TWI unit.
• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit
If set, this bit enables the recognition of a general call given over the 2-wire serial bus.
22.9.6 TWAMR – TWI (Slave) Address Mask Register
• Bits 7:1 – TWAM: TWI Address Mask
The TWAMR can be loaded with a 7-bit slave address mask. Each of the bits in TWAMR can mask (disable) the
corresponding address bits in the TWI address register (TWAR). If the mask bit is set to one then the address match logic
ignores the compare between the incoming address bit and the corresponding bit in TWAR. Figure 22-22 shown the address
match logic in detail.
Figure 22-22. TWI Address Match Logic, Block Diagram
• Bit 0 – Reserved
This bit is an unused bit in the Atmel
®
ATmega48PA/88PA/168PA, and will always read as zero.
Bit 76543210
(0xBA) TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE TWAR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value11111110
Bit 76543210
(0xBD) TWAM[6:0] – TWAMR
Read/Write R/W R/W R/W R/W R/W R/W R/W R
Initial Value00000000
TWAR0
Address
Match
TWAMR0
Address Bit Comparator 6 to 1
Address Bit Comparator 0
Address
Bit 0