Datasheet

205
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
22.7.6 Combining Several TWI Modes
In some cases, several TWI modes must be combined in order to complete the desired action. Consider for example reading
data from a serial EEPROM. Typically, such a transfer involves the following steps:
1. The transfer must be initiated.
2. The EEPROM must be instructed what location should be read.
3. The reading must be performed.
4. The transfer must be finished.
Note that data is transmitted both from master to slave and vice versa. The master must instruct the slave what location it
wants to read, requiring the use of the MT mode. Subsequently, data must be read from the slave, implying the use of the
MR mode. Thus, the transfer direction must be changed. The master must keep control of the bus during all these steps, and
the steps should be carried out as an atomical operation. If this principle is violated in a multi master system, another master
can alter the data pointer in the EEPROM between steps 2 and 3, and the master will read the wrong data location. Such a
change in transfer direction is accomplished by transmitting a REPEATED START between the transmission of the address
byte and reception of the data. After a REPEATED START, the master keeps ownership of the bus. The following figure
shows the flow in this transfer.
Figure 22-19. Combining Several TWI Modes to Access a Serial EEPROM
22.8 Multi-master Systems and Arbitration
If multiple masters are connected to the same bus, transmissions may be initiated simultaneously by one or more of them.
The TWI standard ensures that such situations are handled in such a way that one of the masters will be allowed to proceed
with the transfer, and that no data will be lost in the process. An example of an arbitration situation is depicted below, where
two masters are trying to transmit data to a slave receiver.
Figure 22-20. An Arbitration Example
Several different scenarios may arise during arbitration, as described below:
● Two or more masters are performing identical communication with the same slave. In this case, neither the slave nor
any of the masters will know about the bus contention.
● Two or more masters are accessing the same slave with different data or direction bit. In this case, arbitration will
occur, either in the READ/WRITE bit or in the data bits. The masters trying to output a one on SDA while another
master outputs a zero will lose the arbitration. Losing masters will switch to not addressed slave mode or wait until the
bus is free and transmit a new START condition, depending on application software action.
S
S = START P = STOPR
S
= REPEATED START
PR
S
ASLA + W A A AADDRESS
Master Transmitter
Transmitted from master to slave Transmitted from slave to master
Master Receiver
DATASLA + R
Device 1
Master
Transmitter
SDA
SCL
V
CC
Device n ........ R1 R2
Device 2
Master
Transmitter
Device 3
Slave
Receiver