Datasheet

187
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
22.5 Overview of the TWI Module
The TWI module is comprised of several submodules, as shown in Figure 22-9. All registers drawn in a thick line are
accessible through the AVR data bus.
Figure 22-9. Overview of the TWI Module
22.5.1 SCL and SDA Pins
These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a slew-rate limiter in order to
conform to the TWI specification. The input stages contain a spike suppression unit removing spikes shorter than 50ns. Note
that the internal pull-ups in the AVR pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins,
as explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need for external ones.
22.5.2 Bit Rate Generator Unit
This unit controls the period of SCL when operating in a master mode. The SCL period is controlled by settings in the TWI bit
rate register (TWBR) and the Prescaler bits in the TWI status register (TWSR). Slave operation does not depend on bit rate
or prescaler settings, but the CPU clock frequency in the slave must be at least 16 times higher than the SCL frequency.
Note that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock period. The SCL frequency is
generated according to the following equation:
START/ STOP
Control
Spike
Filter
Slew-rate
Control
Address/ Data Shift
Register (TWDR)
Arbitration detection
Spike Suppression
Bit Rate Register
(TWBR)
Prescaler
Ack
Bus Interface Unit
SCL
Spike
Filter
Slew-rate
Control
SDA
Bit Rate Generator
Address Register
(TWAR)
Address Comparator
Address Match Unit
Status Register
(TWSR)
Control Register
(TWCR)
State Machine and
Status control
Control Unit
TWI Unit
SCL frequency
CPU Clock frequency
16 2(TWBR) PrescalerValue+
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