Datasheet

ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
174
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets
the relationship between data output change and data input sample, and the synchronous clock (XCKn).
20.11.5 UBRRnL and UBRRnH – USART Baud Rate Registers
• Bit 15:12 – Reserved
These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRnH
is written.
• Bit 11:0 – UBRR[11:0]: USART Baud Rate Register
This is a 12-bit register which contains the USART baud rate. The UBRRnH contains the four most significant bits, and the
UBRRnL contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the Transmitter and
Receiver will be corrupted if the baud rate is changed. Writing UBRRnL will trigger an immediate update of the baud rate
prescaler.
Table 20-11. UCSZn Bits Settings
UCSZn2 UCSZn1 UCSZn0 Character Size
0 0 0 5-bit
0 0 1 6-bit
0 1 0 7-bit
0 1 1 8-bit
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 9-bit
Table 20-12. UCPOLn Bit Settings
UCPOLn Transmitted Data Changed (Output of TxDn Pin) Received Data Sampled (Input on RxDn Pin)
0 Rising XCKn edge Falling XCKn edge
1 Falling XCKn edge Rising XCKn edge
Bit 151413121110 9 8
– – – – UBRRn[11:8] UBRRnH
UBRRn[7:0] UBRRnL
76543210
Read/Write
R R R R R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value
00000000
00000000