Datasheet

ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
156
20.3.4 Synchronous Clock Operation
When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input (slave) or clock output
(master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is
that data input (on RxDn) is sampled at the opposite XCKn clock edge of the edge the data output (TxDn) is changed.
Figure 20-3. Synchronous Mode XCKn Timing
The UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling and which is used for data change. As
Figure 20-3 shows, when UCPOLn is zero the data will be changed at rising XCKn edge and sampled at falling XCKn edge.
If UCPOLn is set, the data will be changed at falling XCKn edge and sampled at rising XCKn edge.
20.4 Frame Formats
A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity
bit for error checking. The USART accepts all 30 combinations of the following as valid frame formats:
● 1 start bit
● 5, 6, 7, 8, or 9 data bits
● no, even or odd parity bit
● 1 or 2 stop bits
A frame starts with the start bit followed by the least significant data bit. Then the next data bits, up to a total of nine, are
succeeding, ending with the most significant bit. If enabled, the parity bit is inserted after the data bits, before the stop bits.
When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an
idle (high) state. Figure 20-4 illustrates the possible combinations of the frame formats. Bits inside brackets are optional.
Figure 20-4. Frame Formats
St Start bit, always low.
(n) Data bits (0 to 8).
P Parity bit. Can be odd or even.
Sp Stop bit, always high.
IDLE No transfers on the communication line (RxDn or TxDn). An IDLE line must be
high.
XCK
RxD/ TxD
XCK
UCPOL = 1
UCPOL = 0
RxD/ TxD
Sample
Sample
ST 0 1 2 3 4 [5] [6] [7] [8] (St/ IDLE)(IDLE)
FRAME
[P] Sp1 [Sp2]