Datasheet

ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
144
19. SPI – Serial Peripheral Interface
19.1 Features
● Full-duplex, three-wire synchronous data transfer
● Master or slave operation
● LSB first or MSB first data transfer
● Seven programmable bit rates
● End of transmission interrupt flag
● Write collision flag protection
● Wake-up from idle mode
● Double speed (CK/2) master SPI mode
19.2 Overview
The serial peripheral interface (SPI) allows high-speed synchronous data transfer between the Atmel
®
ATmega48PA/88PA/168PA and peripheral devices or between several AVR devices.
The USART can also be used in Master SPI mode, see Section 21. “USART in SPI Mode” on page 175. The PRSPI bit in
Section 10.10 “Minimizing Power Consumption” on page 37 must be written to zero to enable SPI module.
Figure 19-1. SPI Block Diagram
(1)
Note: 1. Refer to Figure 1-1 on page 3, and Table 14-3 on page 71 for SPI pin placement.
8-Bit Shift Register
Read Data Buffer
SPI Control RegisterSPI Status Register
MSTR
SPI Clock (Master)
SPE
SPI Control
SPI Interrupt
Request
Select
Clock
Logic
MISO
Clock
8
88
S
M
S
M
M
S
MSB LSB
SPIE SPE
WCOL SPIF SPI2X
SPI2X SPR1
MSTR SPE DORD
SPR0
DORD MSTR CPOL CPHA SPR1 SPR0
MOSI
SCK
SS
Divider
/2/4/8/16/32/64/128
XTAL
Internal
Data Bus
Pin
Control
Logic